The use of synchronous rectifiers (SRs) is well established in DC-DC power converters to improve the conduction loss of the output stage. When synchronous rectification is applied to a topology, the resultant power converter is transformed into a two-quadrant converter. As such, the converter can sink and source current.
If a back biased load is applied to the output of a power converter during the startup phase, a condition is created that is analogous to placing two converters in parallel. In this configuration, large circulating currents will flow if the two converters are not perfectly matched in voltage and thus have a negative effect on the load and or the power converter system. Therefore, there exists a need in the art for a manner in which a back bias condition can be detected and tolerated by a two-quadrant power converter during the startup phase when the output of the converter is ramping to its set point level.